spsemi ... www.spsemi.cn page 1 of 3 electro-static discharge for aotomobile ALSD05BT low capacitance esd protection features esd protection:level 4 working voltage : 5v low clamping voltage 100 watts peak pulse power per line(tp=8/20s) ultra low capacitance protection one line i/o port esd/ALSD05BT iec compatibility en61000 -4 iec61000-4-2(esd):level 4,contact:30kv,air:30kv iec61000-4-4(eft):40a -5/50ns iec61000-4-5(surge):4a -8/20s mechanical characteristics jedec 0402 package molding compound flammability rating : ul 94v-o quantity per reel : 10,000pcs reel size : 7 inch lead finish : lead free applications lan equipment video dvi high speed data line ethernet usb 2.0 power and data line protection 0402 pin configuration rev 2017 07 24 aec-q101
spsemi www.spsemi.cn page 2 of 3 parameter symbol value units peak pulse power(tp=8/20s) operating temperature range storage temperature range p pp t j t stg 100 -55~150 -55~150 watts maximum ratings (t =25 unless otherwise specified ) a electrical characteristics (t =25 unless otherwise specified ) a ratings and characteristic curves fig.2 pulse waveform 5 010 30 15 0 10 time( ) s 20 25 20 30 40 50 60 70 80 90 100 110 percent of i pp t=i /2 d pp waveform parameters: tr=8s t =20s d e -1 parameter symbol conditions units min. max. ALSD05BT(marking:none) reverse stand-off voltage reverse breakdown voltage reverse leakage current forward voltage clamping voltage peak pulse current junction capacitance v rwm v br r i f v c v pp i c i/o 5 9.4 90 1.15 12 4 6 pin2 to 1 / pin1 to 2 iz=1ma,pin2 to 1 / pin1 to 2 @v rwm i =15ma f i =1a,tp=8/20s pp tp=8/20s 5.6 v v a v v a f p 0vdc,f=1mhz between i/o pins and gnd fig.1 power derating curve 25 0 50 0 t ,ambient temperature( ) a 75 100 20 40 60 80 100 peak power dissipation (%) 125 150 120 ... esd/ALSD05BT rev 2017 07 24
www.spsemi.cn page 3 of 3 spsemi dimensions(0402) 0402 recommended mounting pad layout 1.20 0.047 0.75 0.030 0.75 0.030 a b c dim a b c d1/d2 millimeters min 0.90 0.50 0.10 max 1.10 0.70 0.60 0.40 min 0.035 0.020 0.004 max 0.043 0.027 0.023 0.016 inches d1 d2 c b ... esd/ALSD05BT application information ALSD05BT i/o i/o i/o i/o ALSD05BT pcb layout recommendations the location and circuit board layout is critical to maximize the effectiveness of the i/o protection circuit. the following guidelines are recommended: locate the protection devices as close as possible to the i/o connector. this allows the protection devices to absorb the energy of the transient voltage before it can be coupled into the adjacent traces on the pcb. minimize the loop area for the high.speed data lines, power and ground lines to reduce the radiated emissions. avoid running protection conductors in parallel with unprotected conductors use ground planes wherever possible to reduce the parasitic capacitance and inductance of the pcb that degrades the effectiveness of a filter device. using shared transient return paths to a common ground point. i/o protection rev 2017 07 24
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